The present invention relates to a process for flattening an epitaxial semiconductor wafer. In particular, the present invention provides a process for improving the global flatness and/or local site flatness of an epitaxial semiconductor wafer comprising a substrate wafer and one or more layers of material deposited on that substrate wafer. It further provides populations of epitaxial semiconductor wafers resulting from this process.
Epitaxy is an important process in the semiconductor material industry for achieving the necessary electrical properties of the semiconductor material. For example, a lightly doped epitaxial layer grown over a heavily doped substrate permits a CMOS device to be optimized for latch up immunity as a result of low resistance of the substrate. Other advantages, such as precise control of the dopant concentration profile and freedom from oxygen are also achieved.
Epitaxial semiconductor wafers used as starting materials for the fabrication of integrated circuits must meet certain surface flatness requirements. Such epitaxial wafers must be particularly flat in order to print circuits on the wafer by, for example, an electron beam-lithographic or photolithographic process. Flatness of the epitaxial wafer in the focal point of the electron beam delineator or optical printer is important for uniform imaging in the electron beam-lithographic and photolithographic processes. The flatness of the epitaxial wafer surface directly impacts device line width capability, process latitude, yield and throughput. The continuing reduction in device geometry and increasingly stringent device fabrication specifications are forcing manufacturers of semiconductor wafers to prepare increasingly flatter epitaxial wafers.
Epitaxial wafers can be characterized for flatness in terms of a global flatness variation parameter (for example, total thickness variation ("TTV") or Total Indicated Reading ("TIR")) or in terms of a local site flatness variation parameter (for example, Site Total Indicated Reading ("STIR") or Site Focal Plane Deviation ("SFPD")). A more detailed discussion of the characterization of wafer flatness can be found in F. Shimura, Semiconductor Silicon Crystal Technology (Academic Press 1989), pp. 191-195.
TTV, frequently used to measure global flatness variation, is the difference between the maximum and minimum thicknesses of the epitaxial wafer. TTV in the wafer is an important indicator of the quality of the polish of the wafer. STIR (back reference center focus), frequently used to measure local site flatness variation, is the sum of the maximum positive and negative deviations of the surface in a small area of the epitaxial wafer from a reference plane which is parallel to the back surface of the wafer and intersects the front surface at the center of the local site. A conventional polished epitaxial semiconductor wafer typically will have a TTV exceeding about 0.7 .mu.m and a STIR (back reference center focus) exceeding about 0.5 .mu.m for any 25 mm.times.30 mm local site. Such values, however, depend upon actual process conditions and often are significantly larger than 0.7 .mu.m or 0.5 .mu.m. Unless otherwise expressly noted, all STIR values discussed herein are based on a back reference center focus reference plane.
In general, epitaxial layers are formed by means such as chemical vapor deposition (CVD), molecular-beam epitaxy (MBE), thermal evaporation or sputtering of silicon under high vacuum conditions. Chemical vapor deposition is commonly used because it is the most flexible and cost efficient method for growing epitaxial layers on semiconductor material. Generally speaking, chemical vapor deposition involves introduction of volatile reactants (e.g., SiCl.sub.4, SiHCl.sub.3, SiH.sub.2 Cl.sub.2 or SiH.sub.4) with a carrier gas (usually hydrogen) into an epitaxial reactor containing a semiconductor wafer or wafers. A layer of the epitaxial material is deposited on the wafer surface. Among the factors affecting epitaxial layer growth on the wafer substrate are the type of reactor, temperature, pressure, gas flow rates and gas flow patterns. Illustrative processes for the preparation of epitaxial semiconductor wafers are disclosed in, for example, U.S. Pat. Nos. 4,926,793; and 4,925,809.
Epitaxial semiconductor wafers prepared according to conventional epitaxy techniques generally have an epitaxial layer thickness in the range of about 1 .mu.m to about 100 .mu.m. The TTV and STIR of a conventional epitaxial wafer typically have values equal to about 1% to about 20% of the thickness of the epitaxial layer. As the thickness of the epitaxial layer increases, the TTV and STIR of the epitaxial wafer generally increase.
Conventional epitaxial techniques do not uniformly deposit the epitaxial layer. For example, epitaxial wafers prepared in a single wafer reactor generally exhibit a radial variation in flatness. In addition, as the thickness of the epitaxial layer grows, it becomes increasingly more difficult to maintain a uniformly flat epitaxial wafer. Therefore, there is a need for new methods capable of further improving the flatness of an epitaxial semiconductor wafer, and/or the yield of a given production run, over conventional values. In addition, there is a need for methods capable of reducing the overall demands and disadvantages of conventional epitaxial wafer preparation processes without degrading wafer flatness.
The process of the present invention uses the appropriate sequencing of an additional material removal tool, preferably a step employing a plasma assisted chemical etching removal tool, to improve the total thickness variation and/or yield of epitaxial semiconductor wafers.
Mumola, U.S. Pat. No. 5,419,803, discusses a method for planarizing microstructures. A microstructure or series of microstructures on a substrate surface is covered by a planarization layer of material which completely covers the microstructures. A plasma assisted chemical etching tool is then used to reduce the overcoat layer, particularly an oxide overcoat layer, to a desired minimum thickness measured with respect to the microstructure having the greatest height above the substrate surface.
Zarowin, et al., U.S. Pat. No. 5,254,830, discusses a method using a thickness measuring apparatus to generate profile data representing the point-by-point thickness of a semiconductor wafer, particularly the thickness of the silicon film of a silicon-on-insulator ("SOI") substrate. The profile data is processed to yield a dwell time versus position map for the entire surface measured. This map is then used to control the movement of a material removal tool over the surface to locally remove additional stock from the surface to produce a layer having a uniform thickness, particularly to produce an SOI wafer having a device layer with a uniform thickness.
Poultney, U.S. Pat. No. 5,563,709, discusses the use of a metrology apparatus, particularly an apparatus which uses Hartmann-Shack Sensor configurations, to measure the total thickness variation of wafers. The metrology apparatus is situated above a flattening apparatus, such as a plasma assisted chemical etching tool. The placement of the metrology apparatus above the flattening apparatus allows the metrology step and material removal step to occur at a single work station and eliminates the need for a sophisticated co-registration scheme for overlapping a metrology map into shaping station coordinates.